Automatic generation of functional coverage models

Abstract

This paper proposes a framework to automatically generate functional coverage model for the Design under Verification (DUV). The coverage goals are identified to cover different combinations of the design inputs, outputs, Finite State Machines (FSMs) valid states/transitions and internal signals that control the guard expressions of the design control flow. Additionally the cross coverage of highly correlated design variables is added to the final coverage model and generated using data mining techniques. The proposed framework illustrates how formal methods can be used to automate the identification of unreachable coverage-points and then automatically generate the exclusion of those coverage items for final accurate coverage results calculations. Formal verification is also utilized to generate test scenarios (counter examples) for reachable coverage goals that have not been covered in initial random simulation runs. Our experimental results demonstrate the effectiveness of the proposed approach in closing the coverage loop for a set of today's RTL designs.