Automatic generation of a parameter-domain-based functional input coverage model

Abstract

IP cores, which are usually described in the RT level, must be thoroughly verified so as not to allow design bugs to inadvertently propagate throughout the system. As the mainstream technique, simulation-based functional verification avoids the state-space explosion issues commonly present in formal verification methodologies. However, since RTL cycle-accurate simulation is relatively slow, the amount of random testing must be limited by completion and sufficiency metrics, identified as the coverage model. The coverage model may be developed after the constrained random stimuli set has been defined, as in a traditional verification flow, or developed before, as in coverage-driven verification. Both approaches make it clear that functional coverage is not a well defined object, whose construction lacks formalism. In the present paper, we propose a strategy to design functional input coverage models on the basis of the PD formalism, by which non-valid input stimuli become evident. Results show that, in contrast to uniform coverage models, PD-coherent coverage models reduce significantly the amount of stimuli wasted on coverage events that, although fulfilled, keep receiving item hits disregarding other less-favored events. Shorter simulation times are achieved for equivalent designs, testbenches, and parameter domains. Also, it can be demonstrated that, as data collected during simulation fits strongly with stimuli generation and functional coverage, it provides information that is easier to interpret, and allows analyzing the DUV's behavior with a relatively higher consistency level.