Automatic Design Flow for Creating a Custom Multi-FPGA Board Netlist

Abstract

Field-Programmable Gate Array (FPGA) is widely used for implementing digital circuits due to its moderately high level of integration and rapid turnaround time. As the cost of masks in IC fabrication is increasing and the performance gap between FPGA and ASIC is reducing, more and more systems will be implemented with FPGAs. A multi-FPGA board, which is a collection of FPGAs, is used in case that the logic capacity of a single FPGA is insufficient. Nowadays, creating a custom multi-FPGA board is mainly a manual process. In this paper, an automatic design flow is proposed to create a multi-FPGA board netlist which is tailored to a specific design. In order to propose an automatic design flow, we assume for this study: 1) All the FPGAs used in the board to implement logic elements of the designs have the same FPGA type (vendor, family, device and package). 2) No information about the position of the FPGAs in the board and no PCB layout generated. The proposed design flow has three steps: the design partitioning, the interconnect synthesis and the design routing. The design partitioning and the design routing can be done respectively by commercial tools provided by Flexras Technologies. An algorithm is developed to do the interconnect synthesis which distributes the inter-FPGA connections according to cut signals of the partitioned design. For the purpose of this study, a testbench generator has been developed. In the experiments, several designs are generated by the testbench generator and several board netlists are generated for each design by varying the used FPGA type. Therefore, the automatic design flow could lower the entry barrier for new board designer. Results show that the proposed automatic design flow reduces significantly the development time, and accelerates the time-to-market of new products with the optimized first-chip cost and improved system frequency. Pareto-optimal solutions for a given design can be selected instantly among the generated board. Then, the most adapted one can be chosen according to specifications of board designers among the Pareto-optimal solutions. When comparing with an off-the-shelf board, the best case achieves a 150% increase in the system frequency with less number of FPGA in the board. Due to that there are many different existing FPGAs in the market, the FPGA type used in the board influences the system frequency. The future work will predict the most adapted custom multi-FPGA board for a given hierarchical design.