Automatic construction of timing diagrams from UML/MARTE models for real-time embedded software

Abstract

Analysis of timing constraints is an essential part in developing real-time embedded software. Performing the timing analysis during the early development phases prevents timing violations and enhances software quality. In the development of real-time embedded software, UML timing diagrams can play a significant role since they can provide not only intuitive specifications for timing constraints, but also valuable information for verifying system requirements. However, as software complexity increases, modeling timing diagrams is becoming difficult and costly. We propose an automated construction approach of timing diagrams from UML sequence diagrams and state machine diagrams with MARTE annotations. The proposed approach enables developers of RTES to save time required for modeling timing diagrams and prevents making mistakes in construction of timing diagrams.