Automatic Configurable Hardware Code Generation for Software-Defined Radios

Lekhobola Tsoeunyane,Simon Winberg,Michael Inggs

doi:10.3390/computers7040053

Lekhobola Tsoeunyane, Simon Winberg + Show 1 more

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https://doi.org/10.3390/computers7040053

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Abstract

The development of software-defined radio (SDR) systems using field-programmable gate arrays (FPGAs) compels designers to reuse pre-existing Intellectual Property (IP) cores in order to meet time-to-market and design efficiency requirements. However, the low-level development difficulties associated with FPGAs hinder productivity, even when the designer is experienced with hardware design. These low-level difficulties include non-standard interfacing methods, component communication and synchronization challenges, complicated timing constraints and processing blocks that need to be customized through time-consuming design tweaks. In this paper, we present a methodology for automated and behavioral integration of dedicated IP cores for rapid prototyping of SDR applications. To maintain high performance of the SDR designs, our methodology integrates IP cores using characteristics of the dataflow model of computation (MoC), namely the static dataflow with access patterns (SDF-AP). We show how the dataflow is mapped onto the low-level model of hardware by efficiently applying low-level based optimizations and using a formal analysis technique that guarantees the correctness of the generated solutions. Furthermore, we demonstrate the capability of our automated hardware design approach by developing eight SDR applications in VHDL. The results show that well-optimized designs are generated and that this can improve productivity while also conserving the hardware resources used.

Highlights

A software-defined radio (SDR) system implements some or all of its physical layer (PHY)functionality in software [1]
To automate hardware generation methods discussed in this work, we developed a compiler framework as depicted in Figure 10 that serves as a low-level intermediate representation (IR) to generate efficient hardware from a domain-specific language (DSL) for SDR
We have presented an approach that automates the integration of Intellectual Property (IP) cores using a static dataflow with access patterns (SDF-AP) model for rapid prototyping of reconfigurable hardware solutions used in the implementation of SDR applications to be deployed on field-programmable gate arrays (FPGAs)-based platforms

Summary

Introduction

A software-defined radio (SDR) system implements some or all of its physical layer (PHY). Functionality in software [1] This makes it more flexible than the rigid traditional radio architecture that relies on analog hardware components to perform radio signal processing functions. Many SDR systems need to support a diverse range of adjustable operations and operating modes, such as support for multiple bands and carriers, multiple standards, and enabling a variety of services [1,2]. High-performance SDR platforms allow for the implementation of this diversity of operations through the use of multiple types of parallel processing resources including FPGAs, DSPs, and GPPs [3]. FPGAs have become a popular means to implement SDR systems as they strike an effective balance between performance and flexibility, essentially trading allowing sacrifices in performance ASICs are faster and more efficient, they are generally not used in these applications, in the case of experimental SDR prototyped systems, for which low-volume bespoke solutions are often used due to their complexity and need for flexibility and customizability [4].

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