Abstract
Abstract This study proposes a method for automatically tiling appropriate Josephson transmission line (JTL) cells for a given set of paths. Digital RSFQ circuits have been commonly designed in a cell-based design environment. The RSFQ cell library contains pre-designed fragments of JTLs as cells. Appropriate JTL cells are selected and tiled. This method formulates the problem as an instance of integer linear programming (ILP). Subsequently, instances are solved using a solver program. The method generates the tiling of cells according to the solver result. The number of Josephson junctions for JTLs, delay of paths, or weighted sum of such parameters is represented as a linear function and can be optimized. The proposed method performed JTL cell-tiling for several circuits, including a full adder. The runtime was within one second.
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