Abstract

This paper describes a sigma-delta (/spl Sigma/-/spl Delta/) synthesizer for Gaussian frequency and minimum shift keying (GFSK/GMSK) modulation. The key innovation is an in-service automatic calibration circuit which tunes the phase locked loop (PLL) to compensate for process tolerance and temperature variation. The PLL, including 1.8 GHz voltage controlled oscillator (VCO), /spl Sigma/-/spl Delta/ modulator, and calibration circuit has been implemented in a 0.6 micron BiCMOS integrated circuit. The test chip achieves 2.5 Mbit/second using GFSK and 5.0 Mbit/second using 4-FSK.

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.