Automatic Algorithm for the Direct Design of Asymmetric Doherty Power Amplifiers

Abstract

This paper presents a novel method for the direct design of asymmetric Doherty power amplifiers (PAs). Single-transistor class F and ${C}$ simulations for the main and auxiliary amplifiers respectively are first performed at both peak and backoff powers using the intrinsic IV characteristics. A 1-D transcendental equation is then solved to create the Doherty prototype at the intrinsic reference planes. The Doherty output combiner at the package reference planes is finally obtained using non-linear embedding. This direct design method is implemented in an automatic algorithm, which produces a functional DPA prototype in typically 95 seconds. A dual-input DPA operating at 2 GHz is fabricated using two identical 15 ${W}$ packaged ${GaN}$ transistors. A drain efficiency of 69% at peak power $(42.9{dBm})$ and 63 % at 9 dB backoff $(33.9{dBm})$ are observed using continuous wave (CW) measurements. The measured gain is above 14 dB. The PA dynamic response is verified with a 10 MHz LTE signal with a 9.9 dB peak to average power ratio (PAPR). 51.3% average efficiency is achieved after linearization with $-45.5dBc$ adjacent channel leakage ratio (ACLR).