Automated Logic Design of Mos Networks

Abstract

With the technological progress of integrated circuits of very large scale integration (VLSI), MOS logic families such as nMOS and C/MOS are becoming increasingly important because large integration size can be attained with MOSFETs (metal-oxide-semiconductor field-effect transistors) due to low power consumption and simple integrated circuit structure.(1) Compared with other logic families, MOS logic families have a unique feature: each MOS logic gate in any logic network can express a negative function.(2) A negative function is a switching function that can be expressed as the complement of a disjunctive (or conjunctive) form of only noncomplemented literals. Examples are \( \overline {{{x}_{1}}\;v\;{{x}_{2}}{{x}_{3}}} ,\overline {{{x}_{1}}{{x}_{2}}\;v\;{{x}_{2}}{{x}_{3}}\;v\;{{x}_{1}}{{x}_{3}}} \), and \( \overline {({{x}_{1}}\;v\;{{x}_{2}})({{x}_{3}}v\;{{x}_{4}}v\;{{x}_{5}})} \). A negative function is more general than the NOR, NAND, AND, or OR operations that a conventional simple logic gate expresses. Logic gates that express negative functions are called negative gates. Thus, for any switching functions, networks of negative gates require no more gates than those of conventional simple logic gates. As a matter of fact, they generally require much less.