Automated datapath synthesis: a compilation approach

Abstract

Automated synthesis of hardware structures from behavioral level specifications is achieving growing importance in the field of chip design. This paper shows the applicability of analysis, optimization and synthesis techniques from conventional compiler construction to the synthesis task. Starting point is a dataflow graph, which is scheduled for execution on a multiprocessor network. The model of two-dimensional graph arrangementis introduced, which is an extension of linear arrangement techniques used in conventional single processor code generation. The scheduling phase generates a two-dimensional arrangement of the input dataflow graph. The subsequent processor mapping and register optimization phase are based on this representation. These synthesis subtask are both implemented by graph coloring algorithms, which are adapted from the compilation area, too. We discuss the integration of additional optimization criteria and how these extensions affect the complexity of the coloring task. Finally, a construction technique for the desired datapath is presented. This technique is based on simple semantics-preserving graph transformation rules.