Automate 3D Modeling of Trace and Via Structures

Abstract

The simulation and modeling of advanced packaging has always been hindered by the duality of the design process. Electrical design packages are based on vectors, plotting, and routing compounds that align well with the physical process of fabricating substrates. However, these design files contain numerous flaws and limitations that does not allow them to be directly imported into modern CAE tools for mechanical, thermal, and electrical modeling and simulation. The resulting gap results in extended model development (physical artifacts are recreated in the CAE software), gross assumptions about composite properties, or a preference for physical testing. This limitation does not align with the strategic goals of the semiconductor packaging industry, especially in regards to the system-in-package and package-on-package technologies. This paper will discuss a new parsing methodology developed to extract trace, via, and ground plots from standard electronic CAD output formats (Gerber, ODB++, ODB.xml). The methodology for capturing trace geometry and eliminating design flaws and singularities will be explained. The process includes selection of appropriate elements for trace, via, power plane, epoxy, and solder mask to ensure successful automesh completion and segmented hole creation and checking to ensure compatibility with model development strategies implemented in Abaqus and Ansys software packages. Identification of material properties through rule checks and computation of effective properties using sandwich and Halpern-Tsai equations will be demonstrated. The presentation will conclude with a discussion on case studies where automated 3D modeling of all copper features provides strong advantages over existing processes, including warpage prediction of wafers, strips, and packages, effective CTE calculations, and high frequency electrical signal simulations.