Abstract
This paper presents an auto-delay offset cancellation technique for time difference repeating amplifier. Pipeline time-to-digital converter (TDC) achieves fine resolution by amplifying the time residue. Therefore the linearity of the time difference amplifier (TA) is important in pipeline TDC. The pulse-train TA, time difference repeating amplifier, was proposed to improve this recently. However, it is hard to get accurate gain in TA because there are many possible mismatch issues. Our work makes the delay offset be cancelled automatically during time difference repetition. The proposed circuit is designed and simulated in 65nm CMOS process. The conversion rate is 100Msps and it has 300ps input time range. The proposed scheme shows the delay offset of about 10fs, which is much less than that of the conventional scheme (∼100ps) under the equivalent device mismatch conditions.
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