Auto Generation of High-Performance Fixed-Point Multiplier for Artificial Neural Networks

Abstract

Multiplier is a critical building block in artificial neural network (ANN). The precision and connection structure of the multiplier should be optimized for an ANN to achieve the best energy, speed and area efficiency. Changes in ANN application and CMOS process often result in the redesign of the multiplier. This paper presents an auto generation method for high-performance fixed-point multiplier based on three techniques, i.e. Modified Booth Encoding (MBE) scheme, improved three-dimensional reduction method (ITDM) and mixed parallel pipelining (MPP). The MBE is customized for ReLU activation function based ANN to remove the sign bit of the multiplicand to save area. The ITDM further shorts the critical path by changing the position of half adder in the conventional TDM. The proposed MPP divides the structures into different stages for parallel and pipelined implementation. The auto generated multiplier speed is 4.04 times faster and the layout is 29% denser and more regular than the conventional MBE combining with TDM method based multiplier.