AUGER: A Tool for Generating Approximate Arithmetic Circuits

Abstract

In recent years, many approximate arithmetic circuits have been proposed to exploit available error resiliency in a wide set of applications. Approximate adders, multipliers, and dividers reduce their original delay, area, power, or energy, as the accuracy of their results is lowered. Due to the diversity of these approximate units and their potential configurations, selecting one that properly fits t o a s pecific de sign re quires to dispose with a vast number of such units already implemented and characterized. Even to propose new approximate arithmetic circuits, it is required to have existing ones available to perform comparisons. In this paper, we present AUGER, a tool to generate and characterize state-of-the-art approximate arithmetic circuits, providing their RTL implementation and a functional model. We validate our tool by presenting examples of its usage and performing analysis with results it produces. AUGER is released as an open-source contribution.