At-speed self-testing of high-performance pipe-lined processing architectures

Abstract

We propose a new methodology for Built-In Self-Test (BIST) where contrary to the traditional scan-path based logic BIST, the proposed solution for test generation does not need any additional hardware, and will not have any impact on the working performance of the system. A class of digital systems organized as pipe-lined signal processing architectures is targeted. The data used for processing in the system are used as test pattern sources. Testing at normal working conditions, and with typically processed data, allows exercise the system on-line and at-speed, facilitating the detection of dynamic faults like delays and cross-talks to achieve high test quality. The proposed new self-test method is free from the negative aspect of over-testing, compared to the traditional logic BIST approaches, and uses a minimal amount of additional hardware. Experimental research was based on the case study of a specialized bio-signal processor architecture, and the results showed promising results in reducing the cost of testing and achieving high fault coverage.