Abstract
Is the current at-speed test methodology good enough to screen delay defects for 65nm and below technologies? Is functional at-speed testing still an option? Or are functional patterns a necessity? Is there an alternative scan-based at-speed test solution? How do we address the existing gap between design flows and at-speed scan pattern generation flow? Is power delivery a limiter for at-speed test? Is it possible to ameliorate at-speed scan test debug problem? Is yield loss a genuine concern for scan-based at-speed test? The proposed panel will examine the pros and cons of at-speed scan tests, and argue whether they can ever take on the role of functional at-speed tests.
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