Atomic Read/Write Registers in the Presence of Byzantine Processes

Abstract

Theorem 18 (stated and proved in Section 5.4) has shown that t < n/2 is an upper bound on the resilience parameter t to build atomic read/write registers in the asynchronous crash process model CAMPn,t\([\emptyset]\). Section 6.3 and Section 6.4 then presented an incremental construction of Single-Writer Multi-Reader (SWMR) and Multi-Writer Multi-Reader (MW-MR) atomic registers.