Atomic Layer Deposition of High-κ Dielectrics on III–V Materials

Abstract

Further dimensional scaling of complementary metal oxide semiconductor devices and circuits requires increasing adoption of new materials, in part, to overcome fundamental performance limitations caused by scaling. III–V semiconductors are among the “new” materials being considered by device researchers for high-performance metal oxide semiconductor field-effect transistors (MOSFETs, see Metal Oxide–Semiconductor Field Effect Transistors). As noted by Antoniadis et al. these materials could provide substantial performance enhancements over Si largely based on their bulk electron mobility (and therefore potential injection velocity) but could also pose many difficult challenges. Perhaps the most difficult and long-standing problem is passivation of the defects that inevitably form between deposited gate insulators and channel materials. We review the literature on atomic layer deposition (ALD) of gate insulators and associated interface passivation approaches that may, with further study and development, lead to practical III–V channel MOSFETs (see Atomic Layer Epitaxy).