ATM cell scheduling by function level evolvable hardware

Abstract

In this paper, we study the possibility of using Evolvable Hardware (EHW) for scheduling real-time traffic in Asynchronous Transfer Mode (ATM) networks. EHW is hardware which is built on programmable logic devices and whose architecture can be reconfigured by using genetic learning to adapt to new environments. A novel design is the function-level EHW [5, 9] based on Field Programmable Gate Array (FPGA) chips, where a number of Programmable Floating processing Units (PFUs) are embedded in one chip. The selectable high-level hardware functions of each PFU make the function-level EHW to be suitable for a wide variety of applications in practice. In our experiment, a statistical multiplexer at an ATM node is modeled for the purpose of generating training data. Superposed bursty cell streams are applied to the model of the multiplexer. The EHW is trained by the collected data in the learning phase. After learning is complete, the best chromosome is tested with respect to various traffic characteristics and the Quality Of Service (QOS) requirements of the cell traffic. Simulation results show that the function-level EHW performs the control well for cell scheduling problem in ATM networks.