Abstract
An additional inner layer for the existing ATLAS Pixel Detector, called Insertable B-Layer (IBL), is under design. The front-end electronics features a new readout ASIC, named FE-I4, which requires new off-detector electronics, currently realized with two VME-based boards: the Back Of Crate module (BOC) implements optical I/O functionality and the ReadOut Driver module (ROD) implements data processing functionality, plus a Timing Interface Module (TIM). This paper presents a proposal for the IBL readout system, mainly focusing on the ROD board.
Highlights
The execution of data fitting using computers allows an improved flexibility for fit code development, since more convenient tools are available compared to the DSP environment. Another idea is to transfer the current ReadOut Driver module (ROD) Master DSP functions to a PowerPC2 core inside a programmable device, in order to have an architecture without DSPs: this has the great advantage of leading to a single design and simulation environment within which both logic and PowerPC software can be verified together
These commercial devices allow to reuse most of the VHDL code that has been designed to implement the firmware on the current ROD card for the ATLAS pixel detector
The PowerPC provides FE-I4 configuration to a command interface block using a serial port with data received from the VME host or from an external PC through a Gbit Ethernet connection, that can be used as a higher speed alternative to the VME bus
Summary
This leads to a data I/O bandwidth as large as 4 times the current ROD board. The proposed architecture for the new ROD card (see Figure 2) is based on the use of modern FPGA devices, while no DSP chip is foreseen.
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