Abstract

The large Hadron collider (LHC) is expected to increase its center-of-mass energy from 13 to 14 TeV for Run 3 scheduled from 2022 to 2024. After Run 3, upgrades for the high-luminosity-LHC (HL-LHC) program are planned and the operation will start in 2027, increasing the instantaneous luminosity to 5.0-7.5 times its nominal luminosity. Continuous upgrades of the ATLAS trigger system are planned to cope with the high event rate and to keep the physics acceptance. During the long shutdown period before Run 3, new detectors will be installed to improve the trigger performance. A new trigger logic, combining information from detectors located outside of the magnetic field and new detectors installed inside the magnetic field, will be introduced for Run 3 to reduce the trigger rate. In order to handle data from the various detectors, a new trigger processor board has been developed and the design is presented. During the upgrade for HL-LHC, the trigger and readout systems of the first level hardware-based part are planned to be upgraded. Full-granularity information will be transferred to the trigger processor board which enables more OFF-line like track reconstruction in the hardware-based system. To handle the full-granularity information and perform the hardware-based track reconstruction, the trigger processor board will be equipped with a field programmable gate array (FPGA) with hundreds of transceivers and a large memory. Expected performance for the hardware-based endcap muon trigger in Run 3 and HL-LHC will also be presented.

Highlights

  • T HE large Hadron collider (LHC) [1] is the world’s largest accelera√tor, of-mass energy of s colliding = 13 TeV protons with a centerand peak instantaneous luminosity of 2.0 ×1034 cm−2s−1

  • A step-by-step upgrade of the hardware-based (Level-1, −0) endcap muon trigger is planned for Run 3 and the HL-LHC to handle higher luminosity

  • The estimated L1 endcap muon trigger rate for a 20 GeV threshold is about 13 kHz at an instantaneous luminosity of 2.0 ×1034 cm−2s−1, which meets the requirements for Run 3

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Summary

INTRODUCTION

The L1 trigger uses a subset of information from the detector to make decisions and reduce the event rate to 100 kHz. The decision is made in 2.5 μs (called the L1 latency). The ATLAS detector will include new hardware-based trigger capabilities for Run 3 and the HL-LHC. New subdetectors will be installed to improve performance and reduce the trigger rate of current triggers. This period is called the Phase-I upgrade. In order to cope with the higher luminosity of the HL-LHC, the trigger and readout systems of the hardware-based trigger are planned to be further upgraded. The trigger latency and rate will be increased to 10 μs and 1 MHz, respectively, by replacing the current system with high-bandwidth readout electronics.

PHASE-I UPGRADE OF THE ATLAS LEVEL-1 MUON TRIGGER
New Coincidence Logic in Run 3
Hardware Design of the Sector Logic Board
Firmware Implementation for the New Coincidence Logic
PHASE-II UPGRADE OF THE ATLAS LEVEL-0 MUON TRIGGER
Performance of Level-1 Endcap Muon Trigger
TGC Track Reconstruction
Firmware Implementation for the TGC Track Reconstruction
Performance of the Level-0 Endcap Muon Trigger
Findings
CONCLUSION
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