Abstract

Timing leakage can be exploited to break a cryptographic system. Even though timing attacks have been well-researched for the past decade, recent system implementations remain highly vulnerable to these attacks. There is a critical need to develop a framework for automatic evaluation of vulnerability of a design against these attacks, so that integrated circuit designers can understand the vulnerability and take appropriate actions to counter them. In this paper, we proposed a novel CAD tool framework for automatic timing attack vulnerability evaluation, referred to as ATAVE, with associated algorithms and metrics. RSA implementation using Montgomery multiplication with square-and-multiply algorithm is efficiently analyzed using ATAVE.

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