Abstract
Defect probabilities in embedded memories have been increased by the scaling reduction in advanced VLSI technology. Built-In Self Repair (BIRA) circuit design is a solution to improve the yield drop and get to a high reliability. This paper will present an at-speed optimal algorithm to repair Word-Oriented memories. In spite of parallel structure in our analyzer to get high analysis speed, the area consumption of the circuit has decreased considerably due to the optimal algorithm. The repair rate of the proposed method is also 100% because of applying the binary search three as its foundation. Simulation results and comparison with other methods show the efficiency of the Wordy-R-CRESTA analyzer method.
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