Abstract
Asynchronous cell-based transmission is the preferred transmission mode for emerging high-speed network standards such as the IEEE 802.6 metropolitan area network standard and the CCITT broadband integrated services digital network. These networks are envisaged to operate at bit rates in excess of 100 Mbit/s. The high bit rate and the cell-based mode of transmission pose challenging requirements on memory-buffer management and the reassembly of packets from constituent cells. The paper describes hardware architecture and memory-management techniques developed to achieve the required packet-reassembly functions and buffer-memory management for a node operating in a high speed asynchronous-transfer-mode-based network. The paper also discusses a number of major generic issues addressed during the development.
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