Asynchronous 2-Phase Level-Encoded Convention Logic (LCL)

Abstract

Asynchronous Quasi-Delay-Insensitive (QDI) circuits, especially Null Convention Logic (NCL), has recently become a very active research area in digital logic design. NCL methodologies eliminate problems related to the distribution of clock trees and can also significantly reduce power consumption, noise and electromagnetic interference (EMI). It has been shown to be the most robust methodology for asynchronous design with an ease-of-use design framework, high level of optimization and integration ability. However, NCL is based on a 4-phase protocol which requires 2 round-trip communications per transaction (one for the data phase and one for the reset phase). Using a 4-phase protocol has the benefit of a relatively simple hardware implementation but leads to lower throughput and higher power consumption which must account for the reset phase. Those limitations prevent a 4-phase approach such as NCL to be applied for high-throughput systems, such as network-on-chip. Our research develops a new NCL-based 2-phase logic template which can operate asynchronously without returning to the reset phase. This novel logic template is called Level-Encoded Convention Logic (LCL). In this paper, the microarchitecture for basic logic elements and the circuit framework of this new template are presented. Furthermore, we will also provide a simple LCL example design, which has been successfully implemented and verified.