Asymptotic limits of video signal processing architectures

Abstract

This paper analyzes the effects of technology scaling on video signal processing (VSP) architectures. We evaluate the processor, the memory, and the interconnect delays in terms of sophisticated delay models (that take into account deep-sub-micron device characteristics) and study how the response times of these logic components are affected when the feature sizes scale down. Equations for gate and interconnect delays, as functions of process scaling, are derived and the impact of these results examined in the context of heavily pipelined architectures, architectures featuring crossbar interconnection networks, and architectures whose performance is dominated by memory bandwidth. Architectural parameters such as clock skew, clock frequency, memory interleaving, memory efficiency, and average waiting times are analyzed in the light of the scaling behavior of the gate and the interconnect delays. In the context of scaling of interconnection lines and memory modules, we also highlight how the transmission-line characteristics of long lines are affected by technology scaling and how the delay associated with the memory subsystem-both the memory interleaving and the memory interconnect network-can be a potential bottleneck for the system's speed of operation. It is likely that sophisticated compilation and scheduling techniques must be employed along with architectural optimizations to achieve maximum system performance and ensure that the final hardware-software configuration does not overload the processor-memory communication.