Asymmetric transistor sizing targeting radiation-hardened circuits

Abstract

This article proposes a technique to improve the dependability of circuits under energetic particle irradiation by resizing transistors in the most critical paths. First, the SET vulnerability of a mapped circuit is analyzed to identify the most sensitive nodes. The sensitivity of the circuit is defined by the logical and electrical masking. Once the most critical nodes are selected, a transistor sizing algorithm is able to resize the pull-up and pull-down transistors separately. The asymmetric resizing offers interesting area and performance trade-off in comparison with gate sizing and gate duplication techniques. Results show very small area and performance penalties for circuits operating at ground level for a 130-nm technology process.