Asymmetric Stencil Approach for Latency Reduction of Real-Time Peak Detection Using AMPD Algorithm and FPGA Technology

Abstract

In many signal processing applications, the detection of peaks is a substantial stage. However, the high false-positive peak identification rate is a crucial problem because of the complexity of the signals and multiple noise sources. For this reason, a modified Automatic Multiscale Peak Detection (AMPD) algorithm of any time serial data based on Field-Programmable Gate Array (FPGA) has been implemented by these authors. In addition, a kind of approximation with an asymmetric stencil is proposed to reduce the pipeline latency. In this paper, it is focused on evaluating the trade-off relationship between latency reduction effects and accuracy of peak point detection on a real-time peak detection method developed in the previous study using the AMPD algorithm and FPGA technology.