Asymmetric sizing: An effective design approach for SRAM cells against BTI aging

Abstract

The rate of aging of ICs is increasing with the continued reduction in feature sizes of devices. Bias temperature instability (BTI) is considered to be the major reliability hazard in nano-scale CMOS and causes stability degradation of SRAM cells. Some of the SRAM cells functioning properly at fabrication may fail during their desired lifetime due to aging. This will cause large aging quality loss. This paper addresses one key characteristic of aging, namely differential aging. This occurs due to the characteristics of data typically stored in SRAMs. After carefully studying the impact of differential aging on SRAM cells, we propose an asymmetric sizing approach for SRAM cells to maximize the probability of correct operation after m months of usage considering process variations. Our experiment results show that the asymmetric design can achieve much better aging quality loss (90× better) with optimal lifetime yield per area compared to the symmetric SRAM cell designs.