Abstract
Partially depleted (PD) 0.15 /spl mu/m CMOS silicon-on-insulator (SOI) SRAMs were exposed to heavy ions, 14 MeV neutrons, and protons. The upset threshold and saturated cross section LET values were determined from heavy ion exposures. The SRAMs were then exposed at various angles of incidence with respect to a 14 MeV neutron source to a total fluence of 4/spl times/10/sup 13/ n/cm/sup 2/. The number of upsets from front exposure was more than double the number from back exposure. Following neutron exposure, proton upset measurements were performed. For a given fluence, the number of proton induced upsets was essentially identical to the number of neutron induced upsets.
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