Asymmetric Gate Schottky-Barrier Graphene Nanoribbon FETs for Low-Power Design

Abstract

The ambipolar behavior limits the performance of Schottky-barrier-type graphene nanoribbon field-effect transistors (SB-GNRFETs). We propose an asymmetric gate (AG) design for SB-GNRFETs, and show that it can significantly reduce the IOFF. Simulation results indicate at least 40% and 5× improvement in the subthreshold swing and the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> /I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ratio, respectively. We build an accurate semianalytical closed-form model for the current-voltage characteristics of SB-GNRFETs. The proposed Simulation Program with Integrated Circuit Emphasis (SPICE)-compatible model considering various design parameters and process variation effects, which enables efficient circuit-level simulations of SB-GNRFET-based circuits. Simulation results of benchmark circuits show that the average energy-delay product of the AG SB-GNRFETs is only ~22% of that of a symmetric gate for the ideal case and ~88% for devices with line edge roughness.