Asymmetric Body Bias Control With Low-Power FD-SOI Technologies: Modeling and Power Optimization

Abstract

Body bias control is a fundamental technique widely used to provide an efficient tradeoff between leakage power and performance in ultralow-power systems. Therefore, a lot of research about power optimization which provides optimal power supply and body bias voltages has been carried out. However, considering the actual voltage sources, the conventional approaches suffer from limited performance/power control granularity and may lead to degradation in terms of the energy efficiency. Therefore, in this paper, a power optimization method that improves the performance/power control granularity is proposed and evaluated with real processor chips. In the proposed optimization, the body biases for nMOSFET and pMOSFET are controlled independently, while the conventional methods control them uniformly. This increases the number of possible voltage combinations and allows finer target frequency selection leading to lower power consumption than the conventional methods at the cost of the optimization complexity. In order to ease this complexity, the proposed optimization is based on simple power and delay models. The model-based optimization does not require brute force search in the phase of real chip testing; thus, the testing time and cost can be significantly reduced. Since the coefficients of the models are extracted with real chip measurements, the error of the model can be suppressed to a few percent in average. The proposed approach is validated by real chips implemented with a 65-nm fully depleted silicon on insulator technology. The evaluation results show that the proposed optimization is an efficient mean of power reduction for a leakage current dominant chip. In fact, when compared with the conventional method, the proposed approach achieves 9.617% of average power reduction reaching up to 22.77% in the case of the V850 microcontroller.