Assessment on the Adequacy of Dual Current Supply in CMOS Dual Differential Amplifier

Abstract

This paper proposed a method, which aims to increase the fault detection and mitigate faults which are identified in CMOS analog and digital circuits. This proposed technique is applied to a typical dual differential CMOS circuits. The proposed test includes a dual current-based test technique, which needs a fault-free circuit which combines with quiescent supply current and transient supply current methods to provide a fault confirmation by providing some known faults. A built-in dual current supply technique, which introduces insignificant performance degradation of the circuit-under-test (Butyrlagin et al. in Design feature of high speed CMOS differential difference op amplifier, 2018 [1]; Soliman and Mahmoud in J Circ Syst Comput 18:1287–1308, 2009 [2]), which is used to filter the power flowing through the all the nodes apparently in the circuit. The testing procedure also increased based on the application of different faults which occurred during fabrication. This approach plays a vital role, in the area of CMOS analog and mixed-signal circuits (Prokopenko et al. in The main connection circuits of the radiation-hardened differential difference amplifier based on the Bipolar and field effect technological process. Don State Technical University, Rostov-on-Don, Russia 2OJSC, Minsk Scientific and Research Institute of Instrument Design, Minsk, Belarus, 2014 [3]). This proposed circuit has been implemented in the mentor graphics 0.25um technology physical design Tanner EDA tool.