Assessment of Thermal-aware Floorplans in a 3D IC for Server Applications

Abstract

Three-dimensional (3D) interconnection technology has been introduced to reduce signal delay and interconnect power loss in various modern electronics platforms [1]–[4]. Therefore, 3D integrated circuit (3D IC) offers a promising solution for high-computing server systems that require faster computing speeds with constrained form-factors. However, critical thermal management challenges such as concentrated thermal stress and thermal coupling, have been arisen as a result of the 3D IC’s higher degree of integration [5]. Herein, we introduce a 3D thermal test vehicle (TTV) to simulate a real microprocessor that consists of logic-SRAM or logic-logic dies. Total of 18 heater blocks are designed to dissipate maximum 1.1 W/mm2 of heat flux and 10 resistance temperature detectors (RTDs) are distributed across each die to acquire local temperature information. Thermal behavior of the TTV has been analyzed under various operating conditions to achieve two main goals: 1) finding the effect of a joint gap, located between top and bottom die of the TTV, on the TTV’s thermal behavior, 2) investigating the effect of floorplans on the temperature change in the heated elements. The response surface methodology, RSM, is used to estimate temperature of the heaters/RTDs, and the estimated temperature data are agreed well with the experimental data within 3% accuracy. In addition, the TTV’s thermal resistance can be fluctuated more than 35% by changing the planar and vertical displacement of the heater blocks due to additional thermal bottleneck and thermal coupling effect, whilst remaining the total dissipated power of 33.6 W. Therefore, the studies in this paper can hint a good thermal management strategy to mitigate thermal stress for the advanced server systems with 3D ICs.