Abstract
Accurate estimation of semiconductors' junction temperature is particularly important that the impact of the temperature on their reliability and performance is evident. The analysis in this paper reveals that the using of RC thermal network models with reduced number of layers can be tremendously useful. Additionally, a simple technique for transforming n-layer Foster model to a one-cell Cauer ladder model is proposed. The one-cell Cauer model implemented by state-space equations can accelerate calculations. This study also presents a finite element method (FEM) validation based on the real IGBT module geometry for the analyses. A buck converter is considered as the case study. The obtained results show that the one-layer Cauer model can provide the exact outcomes. The difference between the thermal impedance curves is considerable; however, both curves have almost the same peak value.
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