Assessing and characterizing inter-and intra-die variation using a statistical metrology framework: A CMP case study

Abstract

As device dimensions continue to shrink below half micron dimensions and the demand for both yield and performance rises, the assessment and control of process and device variation becomes critical. Yield loss from parametric sources will rise unless process margins are characterized to a higher degree than currently available [1]. Process and device variation in VLSI manufacturing occurs with different scope and extent. Process perturbation, drifts, and equipment factors result in lot-to-lot variation, while within-wafer variation may stem from process non-uniformities. While substantial work has focused on the control of lot and wafer-level variation [2], die-level variation has received little attention despite the potential impact on circuit performance [3]. This spatial variation has both systematic and random components. Currently, device variation is often lumped into a single large distribution as part of a “worstcase” approach to modeling. A methodology is needed to transform this large distribution into deterministic components that can be compensated or designed around. We present statistical metrology as a methodology to assess variation and parameterize any resulting circuit and process impact. Variation assessment is achieved by identifying and explicitly modeling the individual sources of variation. The resulting quantification of variation components enables better process modeling, facilitates process control, and provides realistic data for statistical circuit modeling. In this paper we use statistical metrology methods to study inter-level dielectric (ILD) thickness variation for two representative chemical-mechanical polishing (CMP) processes. We suggest that three phases of experimental design are appropriate to (1) identify important factors; (2) construct explicit variation models, and (3) quantify the impact of variation in realistic chip environments. We present a case study in which these phases as well as new modeling methods, in particular a modified form of repeated measure ANOVA (Analysis of Variance), are used to model dieand waferlevel variation for representative CMP/ILD processes. STATISTICAL METROLOGY METHODOLOGY