Assertion based verification of SGMII IP core incorporating AXI Transaction Verification Model

Abstract

In the era of System-on-Chips (SoCs), verification complexity is clearly due to the logical and functional anomalies in the design specifications. Challenges in verification is mainly due to the interoperable multifunctional modules. In most cases, simulation based functional verification validates the system functionalities. But with the progress in technology, tools and methodologies need to be improved to meet the challenges of transforming verification environment. The adoption of System Verilog (SV) based Universal Verification Methodology (UVM) bridges the gap between high-level proposition and low-level details of the design under verification. The intent of this paper is to throw light into benefits associated with Assertion Based Verification (ABV). ABV has been successfully applied to multiple levels of design abstraction. The efficiency of ABV is proven in SGMII IP core integrated to Advanced eXtensible Interface (AXI)-Wishbone(WB) bridge through an AXI Transaction Verification Model (TVM). ABV along with coverage based verification facilitates verification of complete functionalities. All simulations are done in NCsim and waveforms are analysed in Simvision.