Assembly Technology Development for 3D Silicon Stacked Module for Handheld Products

Abstract

The objective of this consortium research work is to develop a 3D SiP based on silicon platform technology for integrating heterogeneous multifunctional devices for handheld products with imaging application. The developed 3D SiP can be used for signal speed of 2Gbps with designed silicon through via structures and matched transmission lines. The thermal performance of the 3D SiP is optimized for 3 watts heat dissipation by natural convection cooling. This paper focuses on the process development of five key assembly technologies used to fabricate the 3D silicon carrier SiP. The five key assembly technologies are: (1) wafer thinning, (2) thin flip chip attach on silicon carrier, (3) ultra low loop wire bonding (4), glass cap fabrication and sealing and (5) carrier stacking. The developed SiP has 3 silicon carriers with 4 flip chip and 1 wire bond die chip attached to them and the carrier is stacked one above the other to form the 3D silicon carrier SiP. Key developments in the five assembly technologies include 8 bumped wafer thinning to 100/spl mu/m, lower flip chip interconnect height between the chip and the carrier down to 35/spl mu/m, 40 to 50/spl mu/m low loop wire bonding on overhang by direct reverse wire bonding method using 1 mil diameter Au wire, investigation of 3 types of thin film metallization for wedge bonding, investigation of two different methods in fabricating glass cap 1, Si-anodic bond glass cap 2, SiUV adhesive bond glass cap and investigation on different types of adhesives for cap sealing.