Assembly process simulation of TSV interposer

Abstract

TSV interposer packaging is one of the most important applications for TSV technology. However, the warpage and residual stress arising from the assembly process of TSV interposer have important influence on the reliability of the package. In this paper, two assembly processes were simulated by using the Finite Element Method, the evolution of the stresses and warpage during assembly were compared to obtain the better process flow. According to the chosen process flow, the reliability of micro bumps during assembly was discussed, it was confirmed that both the structure deformation (including deformation of chip and interposer) and TSV-Cu protrusion have effects on the micro bump reliability, it's necessary to take the relative orientation of the micro bumps, TSVs and underfill fillet into consideration during packaging designation.