Assembly process development of stacked multi-chip leadframe package

Abstract

Driven by customer requirements and the need for cost reduction, high density stacked multi-chip package (MCP) based on leadframe type has been developed in Agere Systems. This MCP integrates one SoC chip with two stacked SDRAM chips. The paper focuses on the assembly process development and finite element analysis of high density multi-chip package based on leadframe. All the experiments in the paper were conducted using a test vehicle with 144 pin TQFP leadframe. Three main processes were evaluated in the experiments, which are die attach, wire bonding and molding. The paper presents some of the challenges for process development such as placement accuracy and epoxy bleed for die attach, ball neck nicking and wire straightness control of reverse bonding for wire bonding and wire sweep for molding. The evaluation results for these three processes are satisfactory. The paper also presents finite element modeling for both stacked MCP and discrete single die packages. The results show that there is no obvious difference on package warpage and thermal/mechanical stress for both packages. Therefore, it is verified that the new established processes for this stacked MCP could be used for actual stacked MCP prototypes build and this stacked MCP is promising for future high volume production.