Assembly Challenge and Solution for GaN on Si substrate

Abstract

Gallium nitride (GaN)-based high-electron-mobility transistor (HEMT) power devices have advantage like high voltage operation, high temperature application and high switch speed compared to the traditional silicon (Si)-based semiconductor devices. Due to GaN high cost, it had development combined on a variety of substrates, including sapphire, silicon carbide (SiC) and silicon (Si). Si substrates have become attractive because of the lower device cost and the ability to use standard semiconductor processing lines. The challenges of GaN on Si substrate are big lattice mismatch and hard characteristic of III–V material. Die sawing is a key process due to the GaN brittle characteristic that can cause chipping and mircocracks that cause bad thermal dissipation for devices.In paper, we optimize dicing capabilities in the Flip Chip Scale Package (FCCSP). Due to GaN layer has higher hardness and melting point than Si substrate, Laser Grooving is recommended to use before the blade saw GaN layer and reduce top chipping. On GaN layer result of Laser Grooving cut is very clean on the topside of the die with no chipping issues. Backside quality is a key monitor item of die sawing due to the excessive force required to break and separate the hard III–V material. This paper finds out a suitable die sawing process parameter to meet backside chipping spec and a competitive result compared to Si die sawing.The characterization analysis is including typical reliability testing (Temperature Cycle Test, un-bias HAST and High Temperature Storage Test) are used as verification monitor items for package. The result shows no delamination and SAT issues in the reliability stage.