ASIC realization and performance evaluation of scalable microprogrammed FIR filters using Wallace tree and Vedic multipliers

Abdullah A Aljuffri,Abdulfattah M Obeid,Anas A Hemaid,Mohammed M Alnahdi,Osamh A Alshaalan,Mohammed S Bensaleh,Syed Manzoor Qasim

doi:10.1109/eeeic.2015.7165480

ASIC realization and performance evaluation of scalable microprogrammed FIR filters using Wallace tree and Vedic multipliers

Abdullah A Aljuffri, Abdulfattah M Obeid + Show 5 more

https://doi.org/10.1109/eeeic.2015.7165480

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Publication Date: Jun 1, 2015

Citations: 11

Affiliation: King Abdulaziz City for Science and Technology

#Finite Impulse Response Filters #Realization Of Finite Impulse Response Filters + Show 8 more

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Abstract

Finite impulse response (FIR) filter is widely used in digital signal processing (DSP) and communication systems. Multiplication is an essential and complex building block used in the realization of FIR filters. In this paper, Wallace tree and Vedic multipliers are used for efficient realization of sequential and parallel scalable microprogrammed FIR filter architectures. The designs are coded in Verilog hardware description language and realized using LFoundry 150nm standard-cell based technology. ASIC realization results are presented and analyzed in order to evaluate the performance of both FIR filters.

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