ASIC Implementation of Area-Efficient, High-Throughput 2-D IIR Filter Using Distributed Arithmetic

Abstract

This paper presents a generalized formulation of 2-D IIR filters using distributed arithmetic (DA) techniques. Based on the DA formulation, two efficient structures for 2-D IIR filters are proposed. Hardware-based look-up table (HLUT) is used in the internal blocks, so the proposed structures are reconfigurable. A novel approach of HLUT sharing, among the various internal blocks of structure, is used to reduce the requirement of adders and memory elements. For higher-order 2-D IIR filter, the complexity of HLUT is reduced by dividing the internal block of 2-D IIR filter into parallel and small block for DA decomposition. Such decomposition for higher-order 2-D IIR filters offers high degree of modularity, parallelism and regularity in building blocks, thereby achieving easier hardware and software implementation. In order to reduce combinational delay in the critical path, pipelining is used in the structures. Since proposed structures are multiplier-less and require lesser number of delays and adders, a significant improvement in chip area, power consumption and throughput can be obtained. Finally with the help of ASIC synthesis results, a comparative analysis is made and the results show that for the filter order 15, the proposed structures offer 69 and 59% reduction in ADP and 79 and 76% reduction in ADP than the earlier reported results for separable and non-separable structures, respectively.