ASIC Implementation of 32 and 64 bit Floating Point ALU using Pipelining

Abstract

The 32-bit and 64-bit Floating point Arithmetic Logic Unit is a main part in the design of computers. The Aim of this paper is high performance through the pipelining concept compared to non-pipelining. This ALU includes all the arithmetic and logical operations. The Pipelined modules are independent of each other. The novelty is to design pipelined modules like left shift, right shift, increment, decrement and logical modules. The Arithmetic pipelined modules are also modified. These modules use single and double precision IEEE 754 standard to carry out the required operation. All modules in the ALU design are realized using Verilog HDL. Test vectors are given to the inputs of the floating point ALU to testify its functionality. The simulation is carried out with ModelSim 6.5b simulator and RTL synthesis is done with RTL Compiler tool in Cadence. Physical design of this architecture is done with SoC Encounter cadence tool in 180nm technology. General Terms Algorithm, Floating point number.