ASIC Implementation and Comparison of Recursive Filter using Different Adders For ECG Application

Abstract

The design of a recursive FIR filter for Electrocardiogram (ECG) and Digital Signal Processing (DSP) applications is presented in this paper. The electrocardiogram (ECG) is a biological signal that is frequently employed and plays a significant role in cardiac analysis. Noise with electrical or electrophysiological roots can often interfere with electrocardiogram signals. Any portable health monitoring device, including a battery-powered ECG device, must be carefully designed while considering challenges such limited device size, power consumption, and cost. The formal recursive filter removes unwanted noise from the ECG signal, but it uses more power and has more regions, so a different, better powerand region-efficient recursive filter is introduced. The most essential element of any electronic device has traditionally been the arithmetic and logic unit. In the most significant advances, an arithmetic and logic unit require an effective algorithmic operation, like multiplication and addition, in order to be significant. The design and efficiency of the recursive filter heavily relies on the adder and multipliers. This Paper involves designing a low area and power efficient recursive filter using different adders like Conditional Sum Adder (CSA), Koggestone (KS) Adder, Divide-and-Conquer Tree (DCT) Adder and Fast-Parallel Adder (FP) and a comparison is made among various factors like power, area and slack. All designs are designed using Verilog HDL, simulated using Cadence NCHDL simulator, synthesized using Genus Synthesis tool and finally GDS II file is taken from Cadence- Innovus tool.