ASIC Implementation and Analysis of Logic BIST Controller for Ripple Carry Adder at Different Technology

Abstract

Logic-Built-In-Self-Test (LBIST) is an architectural methodology that tests the Circuit Under Test (CUT) by itself. An Application Specific Integrated Circuit (ASIC) LBIST method is proposed which generates patterns of weighted pseudorandom tests for the CUT. A technique used for testing combinational blocks, sequential blocks, memories, adders, and other embedded logic blocks is Built In Self Test (BIST). The technique entails to produce the test patterns, given into the circuits that is being tested, and then check the response. LBIST allow testing at fast paced and fault coverage is high. The circuit operates in standard or test phase depending by the test data to the controller. In this paper, we describe an implementing of LBIST controller for a combinational logic ripple carry adder by utilization of Xilinx ISE and ASIC flow in Verilog using cadence tools like genus, innovus in 45nm and 180nm library technology. We proposed operation of the testing of CUT can be stop at any point. It helps us to suspend the generation of the signature, in the test sequence at any desired stage. In this instance, the LBIST circuit is considered to provide logic for keeping and an element of generating Signature. Implemented in such a way that it is functioning the basic operation of CUT if it is fault free. In this LBIST scheme considered two cases, one is without fault in circuit under test other is with fault in circuit under test. We have done physical implementation and analysis of LBIST in 45nm and 180nm technology for power, timing, area and we will observe the effect of technology on the performance of LBIST.