ASIC design for conditional nested loops with predicate registers

Abstract

Time-critical sections of multi-dimensional applications, such as image processing and computational fluid dynamics are, in general, iterative or recursive. Most of these applications require each iteration to be executed under a specific time constraint associated with the data input rate. The design of circuits dedicated to perform such repetitive tasks is highly dependent on optimization techniques to achieve the desired execution time. The existence of branch instructions within the recursive code (loop) may degrade the performance of the optimized code. Branch predication techniques utilize predicate registers to centralise the validity of speculatively computed results and prevent those branch hazards. These registers are significant obstacles in the performance gain achievable by the overlap of successive iterations of nested loops. This paper presents a process of designing and dimensioning those registers while optimizing the computational time of the loop.