Abstract
ReRAM’s low voltage and low current programmability are attractive features to solve the scaling issues of conventional floating gate Flash. However, read instability in ReRAM is a critical issue, due to random telegraph noise (RTN), sensitivity to disturb and retention. In this work, the array-level characteristics of read stability in 50nm AlxOy ReRAM are investigated and a circuit technique to improve stability is proposed and evaluated. First, in order to quantitatively assess memory cell stability, a method of stability characterization is defined. Next, based on this methodology, a proposal to improve read stability, called “stability check loop” is evaluated. The stability check loop is a stability verification procedure, by which, instability improvement of 7×, and read error rate improvement of 40% are obtained.
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