Abstract
El artículo presenta una arquitectura hardware que desarrolla la transformada Wavelet en dos dimensiones sobre una FPGA, en el diseño se buscó un balance entre número de celdas lógicas requeridas y la velocidad de procesamiento. El artículo inicia con una revisión de trabajos previos, después se presentan los fundamentos teóricos de la transformación, posteriormente se presenta la arquitectura propuesta seguida por un análisis comparativo. El sistema se implementó en la FPGA Ciclone II EP2C35F672C6 de Altera utilizando un diseño soportado en el sistema Nios II.
Highlights
The Signals representation using decomposing techniques is an old practice
The Cyclone II EP2C35F672C6 FPGA has an internal memory structure organized in 3 columns containing a total of 105 blocks that provide a storage capacity of 483840 bits and a maximum operating speed of 250MHz, in consequence it will be able to process images with N lower than 220 pixels, it is possible to expand the internal storage using blocks of logical arrangements to store data, it is not recommended since only increase 2047 bytes using all the resources of the FPGA
For the architecture control-unit, a design which is supported in the NIOS II [13] system is used
Summary
The Signals representation using decomposing techniques is an old practice. Approximately two hundred years ago Joseph Fourier proposed the representation of functions by superposition of sinus and cosines, the idea has evolved over time and the most recent research leads us to another type of transformations, between them the Wavelets. Vishwanath et al (1994) present two architectures, the first one consists essentially of a one-dimension module for conversion that is used repeatedly to calculate the 2D -DWT, the advantage of the architecture is its simplicity, but it requires too many memory cells which makes it inconvenient for implementation on a chip, another drawback is the latency required to generate the first output data; the proposed second architecture by Vishwanath et al (1995), consists of a systolic filter that handles the filtering in the horizontal direction, a parallel filter to handle the vertical direction and a storage unit.
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