ARM Dual Core Product Demonstration with 2.5D Through-Silicon-Via (TSV)

Abstract

Through-silicon-via (TSV) package construction offers several silicon integration advantages that are being validated by leading technology providers. This paper will describe a System in Package (SiP) design utilizing two functional system-on-chip (SoC) ARM dual-core Cortex-A9 processors connected across a 2.5D silicon interposer. The test vehicle was designed to demonstrate high speed and high bandwidth communication between multiple chips. The two logic chips were designed by Open Silicon, Inc. and fabricated by GLOBALFOUNDRIES on their 28nm-SLP (Super Low Power) process technology. GLOBALFOUNDRIES also fabricated the 2.5D interposer using their 65nm manufacturing flow. Amkor Technology provided the final assembly utilizing advanced TSV packaging technologies such as copper pillar bumping and mass reflow bonding. This is a pivotal demonstration of the heterogeneous die integration approach. A silicon process node or package interconnect density can either preserve or limit inter-chip communication when comparing SoC versus SiP approaches. Connecting two dual-core Cortex-A9 processors within a single package illustrated the expansion of function through multiple die. The test vehicle also implies that a large IC can be re-architected into smaller constituents to increase yield or design flexibility. By utilizing the best technology node for price and performance, 2.5D packaging can lower overall system cost of ownership or conversely, can expand overall performance through multiple high performance ICs. Chip designers are facing increased complexity and higher costs in order to move to smaller IC geometries and the adoption of 2.5D TSV technology will increase the options of construction (one vs. multiple die/SoCs). Having the flexibility to design with one or multiple die while maintaining high performance levels can offset the real estate costs of advanced nodes, permit silicon die reuse, improve yield and decrease overall product risk. The designer must choose the most appropriate silicon and assembly processes that satisfy the needs of each of the major functions in the overall system. Amkor's assembly process for this key product construction has been demonstrated on a range of products for the communications, graphics and the mobile markets. Process flexibility has been a key factor in addressing different markets and package complexity.